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LTC2365/ltc2366 1 23656f features applications description 1msps/3msps, 12-bit serial sampling adcs in tsot the ltc ? 2365/ltc2366 are 1msps/3msps, 12-bit, sam- pling a/d converters that draw only 2ma and 2.6ma, re- spectively, from a single 3v supply. these high performance devices include a high dynamic range sample-and-hold and a high speed serial interface. the full scale input is 0v to v dd or v ref . outstanding ac performance includes 72db sinad and C80db thd at sample rates of 3msps. the serial interface provides ? exible power management and allows maximum power ef? ciency at low throughput rates. these devices are available in tiny 6- and 8-lead tsot-23 packages. the serial interface, tiny tsot-23 package and extremely high sample rate-to-power ratio make the LTC2365/ltc2366 ideal for compact, low power, high speed systems. the high impedance single-ended analog input and the ability to operate with reduced spans (down to 1.4v full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. single 3v supply, 3msps, 12-bit sampling adc n 12-bit resolution n 1msps/3msps sampling rates n low noise: 73db snr n low power dissipation: 6mw n single supply 2.35v to 3.6v operation n no data latency n sleep mode with 0.1a typical supply current n dedicated external reference (tsot23-8) n 1v to 3.6v digital output supply (tsot23-8) n spi/microwire ? compatible serial i/o n guaranteed operation from C40c to 125c n 6- and 8-lead tsot-23 packages n communication systems n data acquisition systems n handheld terminal interface n medical imaging n uninterrupted power supplies n battery operated systems n automotive 1mhz sine wave 8192 fft plot 12-bit tsot23-6/-8 adc family data output rate 3msps 1msps 500ksps 250ksps 100ksps part number ltc2366 LTC2365 ltc2362 ltc2361 ltc2360 typical application l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. v dd v ref gnd a in ltc2366 23656 ta01 analog input 0v to 3v 3v 10f 4.7f serial data link to asic, pld, mpu, dsp or shift registers digital output supply 1v to 3.6v cs sdo sck ov dd input frequency (khz) 0 0 C20 C40 C60 C80 C100 C120 C140 750 1250 23656 ta01b 250 500 1000 1500 magnitue (db) v dd = 3v f smpl = 3msps f in = 994khz sinad = 72db thd = C80.3db www.datasheet.in
LTC2365/ltc2366 2 23656f absolute maximum ratings supply voltage (v dd , ov dd ) .....................................4.0v v ref and analog input voltage (note 3) .........................................C0.3v to (v dd + 0.3v) digital input voltage ......................C0.3v to (v dd + 0.3v) digital output voltage ...................C0.3v to (v dd + 0.3v) power dissipation ...............................................100mw (notes 1, 2) lead free finish tape and reel (mini) tape and reel part marking* package description temperature range ltc2366cts8#trmpbf ltc2366cts8#trpbf ltcyz 8-lead plastic tsot-23 0c to 70c ltc2366its8#trmpbf ltc2366its8#trpbf ltcyz 8-lead plastic tsot-23 C40c to 85c ltc2366hts8#trmpbf ltc2366hts8#trpbf ltcyz 8-lead plastic tsot-23 C40c to 125c ltc2366cs6#trmpbf ltc2366cs6#trpbf ltcxk 6-lead plastic tsot-23 0c to 70c ltc2366is6#trmpbf ltc2366is6#trpbf ltcxk 6-lead plastic tsot-23 C40c to 85c ltc2366hs6#trmpbf ltc2366hs6#trpbf ltcxk 6-lead plastic tsot-23 C40c to 125c LTC2365cts8#trmpbf LTC2365cts8#trpbf ltdcb 8-lead plastic tsot-23 0c to 70c LTC2365its8#trmpbf LTC2365its8#trpbf ltdcb 8-lead plastic tsot-23 C40c to 85c LTC2365hts8#trmpbf LTC2365hts8#trpbf ltdcb 8-lead plastic tsot-23 C40c to 125c LTC2365cs6#trmpbf LTC2365cs6#trpbf ltdcc 6-lead plastic tsot-23 0c to 70c LTC2365is6#trmpbf LTC2365is6#trpbf ltdcc 6-lead plastic tsot-23 C40c to 85c LTC2365hs6#trmpbf LTC2365hs6#trpbf ltdcc 6-lead plastic tsot-23 C40c to 125c trm = 500 pieces. *temperature grades are identi? ed by a label on the shipping container. consult ltc marketing for information on lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ operating temperature range LTC2365c/ltc2366c ............................... 0c to 70c LTC2365i/ltc2366i .............................. C40c to 85c LTC2365h/ltc2366h (note 13) ......... C40c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c v dd 1 v ref 2 gnd 3 a in 4 8 cs 7 sck 6 sdo top view ts8 package 8-lead plastic tsot-23 5 ov dd t jmax = 150c, ja = 250c/w v dd 1 gnd 2 a in 3 6 cs 5 sdo 4 sck top view s6 package 6-lead plastic tsot-23 t jmax = 150c, ja = 250c/w order information pin configuration www.datasheet.in
LTC2365/ltc2366 3 23656f the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) converter characteristics parameter conditions LTC2365 ltc2366 units min typ max min typ max resolution (no missing codes) l 12 12 bits integral linearity error (note 5, 6) l 0.25 1 0.25 1 lsb differential linearity error (note 6) l 0.25 1 0.25 1 lsb transition noise (note 7) 0.34 0.34 lsb rms offset error (note 6) l 2 3.5 2 3.5 lsb gain error (note 6) l 1 2 1 2 lsb total unadjusted error s6 package (note 6) ts8 package (note 6) l l 2 3 3.5 4.5 2 3 3.5 4.5 lsb lsb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) analog inputs symbol parameter conditions min typ max units v in analog input voltage s6 package ts8 package l l C0.05 C0.05 v dd + 0.05 v ref + 0.05 v v i in analog input leakage current cs = high l 1 a c in analog input capacitance between conversions during conversions 20 4 pf pf v ref reference input voltage ts8 package l 1.4 v dd + 0.05 v i ref reference input leakage current ts8 package l 1 a c ref reference input capacitance ts8 package 4 pf t ap sample-and-hold aperture delay time 1 ns t jitter sample-and-hold aperture delay time jitter 0.3 ns dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions LTC2365 ltc2366 units min typ max min typ max sinad signal-to-(noise + distortion) ratio f in = 1mhz l 68 72 68 71 db snr signal-to-noise ratio f in = 1mhz l 70 73 69 72 db thd total harmonic distortion f in = 1mhz l C86 C72 C80 C72 db sfdr spurious free dynamic range f in = 1mhz 87 82 imd intermodulation distortion f in1 = 0.97mhz, f in2 = 1mhz for ltc2366 f in1 = 97khz, f in2 = 100khz for LTC2365 C76 C71.5 db full power bandwidth at 3db at 0.1db 30 5 50 8 mhz mhz full linear bandwidth sinad 68db 2 2.5 mhz www.datasheet.in
LTC2365/ltc2366 4 23656f the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) digital inputs and digital outputs symbol parameter conditions min typ max units v ih high level input voltage 2.7v < v dd 3.6v 2.35v v dd 2.7v l l 2 1.7 v v v il low level input voltage 2.7v < v dd 3.6v 2.35v v dd 2.7v l l 0.8 0.7 v v i ih high level input current v in = v dd l 2.5 a i il low level input current v in = 0v l C2.5 a c in digital input capacitance 2pf v oh high level output voltage v dd = 2.35v to 3.6v, i source = 200a l v dd C0.2 v v ol low level output voltage v dd = 2.35v to 3.6v, i sink = 200a l 0.2 v i oz hi-z output leakage cs = v dd l 3 a c oz hi-z output capacitance cs = v dd 4pf i source output source current v out = 0v C10 ma i sink output sink current v out = v dd 10 ma power requirement symbol parameter conditions min typ max units v dd supply voltage l 2.35 3.0 3.6 v o vdd digital output supply voltage l 1 3.6 v i dd supply current, static mode operational mode, ltc2366 operational mode, LTC2365 sleep mode sleep mode cs = 0v, sck = 0v or v dd f smpl = 3msps f smpl = 1msps C40c to +85c +85c to +125c l l l l 1 2.6 2 0.1 4 3.5 2 5 ma ma ma a a p d power dissipation, static mode operational mode, ltc2366 operational mode, LTC2365 sleep mode sleep mode cs = 0v, sck = 0v or v dd f smpl = 3msps f smpl = 1msps C40c to +85c +85c to +125c l l l l 7.8 6 0.3 3.6 14.4 12.6 7.2 18 mw mw mw w w www.datasheet.in
LTC2365/ltc2366 5 23656f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: when this pin, a in , is taken below gnd or above v dd , it will be clamped by internal diodes. these products can handle input currents greater than 100ma below gnd or above v dd without latchup. note 4: v dd = ov dd = v ref = 2.35v to 3.6v, f smpl = f smpl(max) and f sck = f sck(max) unless otherwise speci? ed. note 5: integral linearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: linearity, offset and gain speci? cations apply for a single-ended a in input with respect to gnd. note 7: typical rms noise at code transitions. note 8: guaranteed by characterization. all input signals are speci? ed with t r = t f = 2ns (10% to 90% of v dd ) and timed from a voltage level of 1.6v. note 9: all timing speci? cations given are with a 10pf capacitance load. with a capacitance load greater than this value, a digital buffer or latch must be used. note 10: minimum f sck at which speci? cations are guaranteed. note 11: the time required for the output to cross the v ih or v il voltage. note 12: guaranteed by design, not subject to test. note 13: high temperatures degrade operating lifetimes. operating lifetime is derated at temperatures greater than 105c. symbol parameter conditions LTC2365 ltc2366 units min typ max min typ max f smpl(max) maximum sampling frequency (notes 8, 9) l 1 3 mhz f sck shift clock frequency (notes 8, 9, 10) l 0.5 16 0.5 48 mhz t sck shift clock period l 62.5 2000 20.8 2000 ns t throughput minimum throughput time, t acq + t conv l 1000 333 ns t acq acquisition time l 181.5 56 ns t conv conversion time l 818.5 277 ns t quiet sdo hi-z state to cs (notes 8, 9) l 44 ns t 1 minimum positive or negative cs pulse width (notes 8) l 44 ns t 2 sck setup time after cs (notes 8) l 6 2000 6 2000 ns t 3 sdo enabled time after cs (notes 9, 11, 12) l 44ns t 4 sdo data valid access time after sck (notes 8, 9, 11) l 15 15 ns t 5 sck low time l 40% 40% t sck t 6 sck high time l 40% 40% t sck t 7 sdo data valid hold time after sck (notes 8, 9, 11) l 55 ns t 8 sdo into hi-z state time after sck (notes 9, 12) l 5 30 5 14 ns t 9 sdo into hi-z state time after cs (notes 9, 12) l 4.2 4.2 ns t power-up power-up time from sleep mode see sleep mode section l 1000 333 ns timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) www.datasheet.in
LTC2365/ltc2366 6 23656f t a = 25c, v dd = ov dd = v ref (LTC2365, note 4) typical performance characteristics integral nonlinearity vs output code differential nonlinearity vs output code integral and differential nonlinearity vs supply voltage histogram for 16384 conversions snr vs input frequency sinad vs input frequency thd vs input frequency thd vs input resistance 461khz sine wave 8192 fft plot output code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 1024 2048 23656 g01 C0.6 0.6 0.8 0.2 3072 4096 v dd = 3v output code 0 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 1024 2048 23656 g02 C0.6 0.6 0.8 0.2 3072 4096 v dd = 3v supply voltage (v) 2.1 inl and dnl (lsb) 0.2 0.6 1.0 3.3 23656 g03 C0.2 C0.6 0 0.4 0.8 C0.4 C0.8 C1.0 2.4 2.7 3.0 3.6 min dnl max dnl min inl max inl code 2045 0 count 2000 4000 6000 8000 10000 2046 2047 2048 2049 23656 g04 2050 v dd = 3v input frequency (khz) 100 snr (db) 72.9 73.1 23656 g05 72.7 72.5 1000 73.5 73.3 v dd = 2.35v v dd = 3.6v v dd = 3v input frequency (khz) 100 72.0 sinad (db) 72.2 72.4 72.6 72.8 73.0 73.2 1000 23656 g06 v dd = 2.35v v dd = 3.6v v dd = 3v input frequency (khz) 100 C84 C83 C81 23656 g07 C85 C86 1000 C87 C88 C82 thd (db) v dd = 2.35v v dd = 3.6v v dd = 3v r in = 10 f smpl = 1msps input resistance () 0 thd (db) C81 C80 100 23656 g08 C82 C83 25 50 75 C78 C79 v dd = 3v f smpl = 1msps f in = 1mhz input frequency (khz) 0 C40 C20 0 400 23656 g09 C60 C80 100 200 300 500 C100 C120 C140 magnitude (db) v dd = 3v f smpl = 1msps f in = 461khz sinad = 72.8db thd = C86.1db www.datasheet.in
LTC2365/ltc2366 7 23656f t a = 25c, v dd = ov dd = v ref (ltc2366, note 4) typical performance characteristics integral nonlinearity vs output code differential nonlinearity vs output code integral and differential nonlinearity vs supply voltage histogram for 16384 conversions snr vs input frequency sinad vs input frequency thd vs input frequency thd vs input resistance 1mhz sine wave 8192 fft plot output code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 1024 2048 23656 g10 C0.6 0.6 0.8 0.2 3072 4096 v dd = 3v output code 0 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 1024 2048 23656 g11 C0.6 0.6 0.8 0.2 3072 4096 v dd = 3v supply voltage (v) 2.1 inl and dnl (lsb) 0.2 0.6 1.0 3.3 23656 g12 C0.2 C0.6 0 0.4 0.8 C0.4 C0.8 C1.0 2.4 2.7 3.0 3.6 min inl max dnl min dnl max inl code 2045 0 count 2000 4000 6000 8000 10000 2046 2047 2048 2049 23656 g13 2050 v dd = 3v input frequency (khz) 100 snr (db) 72.6 72.8 23656 g14 72.4 72.2 1000 1500 73.2 73.0 v dd = 2.35v v dd = 3.6v v dd = 3v input frequency (khz) 100 70.0 sinad (db) 70.5 71.0 71.5 72.0 72.5 73.0 1000 1500 23656 g15 v dd = 2.35v v dd = 3.6v v dd = 3v input frequency (khz) 100 thd (db) C80 C78 -76 1500 23656 g16 C82 C84 C88 1000 C86 C72 C74 v dd = 2.35v v dd = 3.6v v dd = 3v r in = 10 f smpl = 3msps input resistance () 0 C70 C68 C64 75 23656 g17 C72 C74 25 50 100 C76 C78 C66 thd (db) v dd = 3v f smpl = 3msps f in = 1.5mhz input frequency (khz) 0 0 C20 C40 C60 C80 C100 C120 C140 750 1250 23656 g18 250 500 1000 1500 magnitue (db) v dd = 3v f smpl = 3msps f in = 994khz sinad = 72db thd = C80.3db www.datasheet.in
LTC2365/ltc2366 8 23656f typical performance characteristics supply current vs sck frequency input power bandwidth t a = 25c, v dd = ov dd = v ref (LTC2365/ltc2366, note 4) reference current vs sck frequency (ts8 package) integral and differential nonlinearity vs reference voltage (ts8 package) integral and differential nonlinearity vs reference voltage (ts8 package) sck frequency (mhz) 0 0 i dd (ma) 0.5 1.0 1.5 2.0 2.5 3.0 10 20 30 40 23656 g19 50 v dd = 2.35v v dd = 3.6v v dd = 3v sck frequency (mhz) 0 reference current (a) 150 200 250 40 23656 g20 100 50 0 51015 20 25 30 35 45 50 v dd = 2.35v v dd = 3.6v v dd = 3v 16 scks per conversion reference voltage (v) 0.6 nonlinearity error (lsb) 0.2 0.6 1.0 3.0 23656 g21 C0.2 C0.6 0 0.4 0.8 C0.4 C0.8 C1.0 1.2 1.8 2.4 3.6 min dnl max dnl min inl max inl LTC2365, v dd = 3.6v reference voltage (v) 0.6 nonlinearity error (lsb) 0.2 0.6 1.0 3.0 23656 g22 C0.2 C0.6 0 0.4 0.8 C0.4 C0.8 C1.0 1.2 1.8 2.4 3.6 min dnl max dnl min inl max inl ltc2366, v dd = 3.6v input frequency (mhz) 1 C10 magnitude (db) C8 C6 C4 C2 0 2 10 100 23656 g23 v dd = 3v ltc2366 LTC2365 www.datasheet.in
LTC2365/ltc2366 9 23656f pin functions LTC2365/ltc2366 (s6 package) v dd (pin 1): positive supply. the v dd range is 2.35v to 3.6v. v dd also de? nes the input span of the adc, 0v to v dd . bypass to gnd and to a solid ground plane with a 10f ceramic capacitor (or 10f tantalum in parallel with 0.1f ceramic). gnd (pin 2): ground. the gnd pin must be tied directly to a solid ground plane. a in (pin 3): analog input. a in is a single-ended input with respect to gnd with a range from 0v to v dd . sck (pin 4): shift clock input. the sck serial clock ad- vances the conversion process. sdo data transitions on the falling edge of sck. sdo (pin 5): three-state serial data output. the a/d conversion result is shifted out on sdo as a serial data stream with msb ? rst. the data stream consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros. cs (pin 6): chip select input. this active low signal starts a conversion on the falling edge and frames the serial data transfer. LTC2365/ltc2366 (ts8 package) v dd (pin 1): positive supply. the v dd range is 2.35v to 3.6v. bypass to gnd and to a solid ground plane with a 10f ceramic capacitor (or 10f tantalum in parallel with 0.1f ceramic). v ref (pin 2): reference input. v ref de? nes the input span of the adc, 0v to v ref and the v ref range is 1.4v to v dd . bypass to gnd and to a solid ground plane with a 4.7f ceramic capacitor (or 4.7f tantalum in parallel with 0.1f ceramic). gnd (pin 3): ground. the gnd pin must be tied directly to a solid ground plane. a in (pin 4): analog input. a in is a single-ended input with respect to gnd with a range from 0v to v ref . ov dd (pin 5): output driver supply for sdo. the ov dd range is 1v to 3.6v. bypass to gnd and to a solid ground plane with a 4.7f ceramic capacitor (or 4.7f tantalum in parallel with 0.1f ceramic). sdo (pin 6): three-state serial data output. the a/d conversion result is shifted out on sdo as a serial data stream with msb ? rst. the data stream consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros. sck (pin 7): shift clock input. the sck serial clock ad- vances the conversion process. sdo data transitions on the falling edge of sck. cs (pin 8): chip select input. this active low signal starts a conversion on the falling edge and frames the serial data transfer. www.datasheet.in
LTC2365/ltc2366 10 23656f block diagram figure 1. sdo into hi-z state after sck falling edge figure 2. sdo data valid hold time after sck falling edge figure 3. sdo data valid access time after sck falling edge 23656 bd C + + + 4 1 2 s & h v ref 3 gnd a in analog input range ov to v ref 12-bit adc ts8 package 10f 6 7 8 timing logic v dd + 5 4.7f 4.7f ov dd sdo sck three- state serial output port cs sck 1.6v sdo 23656 td01 hi-z t 8 sck sdo 23656 td02 v ih v il 1.6v t 7 sck sdo 23656 td03 v oh v ol 1.6v t 4 timing diagrams www.datasheet.in
LTC2365/ltc2366 11 23656f dc performance the noise of an adc can be evaluated in two ways: signal- to-noise ratio (snr) in the frequency domain and histogram in the time domain. the LTC2365/ltc2366 excel in both. figures 5 and 6 demonstrate that the LTC2365/ltc2366 have an snr of over 72db. the noise in the time domain histogram is the transition noise associated with a 12-bit resolution adc which can be measured with a ? xed dc signal applied to the input of the adc. the resulting output codes are collected over a large number of conversions. the shape of the distribution of codes will give an indication of the magnitude of the transition noise. in figure 4, the distribution of output codes is shown for a dc input that has been digitized 16384 times. the distribution is gaus- sian and the rms code transition is about 0.34lsb. this corresponds to a noise level of 72.7db relative to a full scale of 3v. applications information dynamic performance the LTC2365/ltc2366 have excellent high speed sampling capability. fast fourier transform (fft) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. figures 5 and 6 show typical LTC2365 and ltc2366 fft plots respectively. figure 5. LTC2365 fft plot figure 4. histogram for 16384 conversions figure 6. ltc2366 fft plot code 2045 0 count 2000 4000 6000 8000 10000 2046 2047 2048 2049 23656 f04 2050 v dd = 3v input frequency (khz) 0 C40 C20 0 400 23656 f05 C60 C80 100 200 300 500 C100 C120 C140 magnitude (db) v dd = 3v f smpl = 1msps f in = 461khz sinad = 72.8db thd = C86.1db input frequency (khz) 0 0 C20 C40 C60 C80 C100 C120 C140 750 1250 23656 f06 250 500 1000 1500 magnitue (db) v dd = 3v f smpl = 3msps f in = 994khz sinad = 72db thd = C80.3db www.datasheet.in
LTC2365/ltc2366 12 23656f signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 6 shows a typical fft with a 3mhz sam- pling rate and a 1mhz input. the dynamic performance is excellent for input frequencies up to and beyond the nyquist frequency of 1.5mhz. effective number of bits the effective number of bits (enob) is a measurement of the resolution of an adc and is directly related to sinad by the equation: enob = (sinad C 1.76)/6.02 where enob is the effective number of bits of resolu- tion and sinad is expressed in db. at the maximum sampling rate of 3mhz, the ltc2366 maintains enob above 11 bits up to the nyquist input frequency of 1.5mhz (refer to figure 7). total harmonic distortion the total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log v 2 2 + v 3 2 + v 4 2 + ...v n 2 v 1 where v 1 is the rms amplitude of the fundamental frequency and v 2 through v n are the amplitudes of the second through nth harmonics. thd versus input fre- quency is shown in figure 8. the ltc2366 has excellent distortion performance up to the nyquist frequency and beyond. figure 8. ltc2366 distortion vs input frequency applications information figure 7. ltc2366 enob and sinad vs input frequency input frequency (khz) 100 70.0 sinad (db) enob 70.5 71.0 71.5 72.0 72.5 73.0 11.34 11.50 11.67 11.83 1000 1500 23656 f07 v dd = 2.35v v dd = 3.6v v dd = 3v input frequency (khz) 100 thd (db) C80 C78 C76 1500 23656 f08 C82 C84 C88 1000 C86 C72 C74 v dd = 2.35v v dd = 3.6v v dd = 3v r in = 10 www.datasheet.in
LTC2365/ltc2366 13 23656f applications information figure 9b. ltc2366 intermodulation distortion plot intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermoduation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies f a and f b are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mf a nf b , where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (f a f b ). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd(f a f b ) = 20log amplitude at (f a f b ) amplitude at f a the LTC2365/ltc2366 have good imd as shown in figure 9a and figure 9b respectively. peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of reconstructed fundamental is reduced by 3db for full-scale input signal. the full-linear bandwidth is the input frequency at which the sinad has dropped to 68db (11 effective bits). the LTC2365/ltc2366 have been designed to optimize input bandwidth, allowing the adc to undersample input sig- nals with frequencies above the converters nyquist fre- quency. the noise ? oor stays very low at high frequencies; sinad becomes dominated by distortion at frequencies far beyond nyquist. figure 9a. LTC2365 intermodulation distortion plot input frequency (khz) 0 C140 magnitude (db) C120 C80 C60 C40 0 50 250 350 23656 f09a C100 C20 200 450 500 100 150 300 400 v dd = 3v f smpl = 1msps f b = 396khz f b = 424khz imd = C73.5db input frequency (khz) 0 0 C20 C40 C60 C80 C100 C120 C140 750 1250 23656 f09b 250 500 1000 1500 magnitue (db) v dd = 3v f smpl = 3msps f a = 935khz f b = 1.045khz imd = C71.5db www.datasheet.in
LTC2365/ltc2366 14 23656f figure 10. LTC2365/ltc2366 serial interface timing diagram applications information overview the LTC2365/ltc2366 use a successive approximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 12-bit serial output. both devices operate from a single 2.35v to 3.6v supply. the ltc2366 samples at a rate of 3msps with a 48mhz clock while the LTC2365 samples at a rate of 1msps with a 16mhz clock. the LTC2365/ltc2366 contain a 12-bit, switched-capacitor adc, a sample-and-hold, and a serial interface (see block diagram) and are available in tiny 6- and 8-lead tsot-23 packages. the devices provide sleep mode control through the serial interface to save power during inactive periods (see the sleep mode section). the s6 package of the LTC2365/ltc2366 uses v dd as the reference and has an analog input range of 0v to v dd . the adc samples the analog input with respect to gnd and outputs the result through the serial interface. the ts8 package provides two additional pins: a reference input pin, v ref , and an output supply pin, ov dd . the adc can operate with reduced spans down to 1.4v and achieve 342v resolution. ov dd controls the output swing of the digital output pin, sdo, and allows the device to com- municate with 1.8v, 2.5v or 3v digital systems. serial interface the LTC2365/ltc2366 communicate with microcontrollers, dsps and other external circuitry via a 3-wire interface. figure 10 shows the serial interface timing diagram, while figures 11 and 12 detail the timing diagrams of conversion cycles in 14 and 16 sck cycles respectively. data transfer a falling cs edge starts a conversion and frames the se- rial data transfer. sck provides the conversion clock and controls the data transfer during the conversion. cs going low clocks out the ? rst leading zero and sub- sequent sck falling edges clock out the remaining data, beginning with the second leading zero. (therefore, the ? rst sck falling edge captures the ? rst leading zero and clocks out the second leading zero). the timing diagram in figure 12 shows that the ? nal bit in the data transfer is valid on the 16th falling edge, since it is clocked out on the previous 15th falling edge. in applications with a slower sck, it is possible to capture data on each sck rising edge. in such cases, the ? rst fall- ing edge of sck clocks out the second leading zero and can be captured on the ? rst rising edge. however, the ? rst leading zero clocked out when cs goes low is missed as shown in figures 11 and 12. in figure 12, the 15th falling edge of sck clocks out the last bit and can be captured on the 15th rising sck edge. if cs goes low while sck is low, then cs clocks out the ? rst leading zero and can be captured on the sck rising edge. the next sck falling edge clocks out the second leading zero and can be captured on the following rising edge as shown in in figure 10. 1 sck sdo t 2 t 3 t 4 t 7 t 5 t 8 zero zero b11 b10 b9 b1 b0 zero zero 234 (msb) hi-z state 513141516 t 6 t quiet t acq 13t sck t throughput t conv cs t 1 23656 f10 www.datasheet.in
LTC2365/ltc2366 15 23656f figure 11. LTC2365/ltc2366 serial interface timing diagram for 14 sck cycles figure 12. LTC2365/ltc2366 serial interface timing diagram for 16 sck cycles applications information achieving 3msps sample rate with ltc2366 cs going low places the sample-and-hold into hold mode and starts a conversion. the LTC2365/ltc2366 require at least 14 sck cycles to ? nish the conversion. the conversion terminates after the 13th falling sck edge, which clocks out b0. the 14th falling sck edge places the sample-and-hold back into sample mode. ignoring the last two trailing zeros, the user can bring cs high after the 14th falling sck edge. the user can also keep the last two trailing zeros by bringing cs high right after the 16th falling sck. in both cases, a sample rate of 3msps can be achieved by using a 48mhz sck clock on the ltc2366, where t throughput is 333ns. serial data output (sdo) the sdo output remains in the high impedance state while cs is high. the falling edge of cs starts the conversion and enables sdo. the a/d conversion result is shifted out on the sdo pin as a serial data stream with the msb ? rst. the data stream consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros. the sdo output returns to the high impedance state at the 16th falling edge of sck or sooner by bringing ? c ? s high before the 16th falling edge of sck. the output swing on the sdo pin is controlled by the v dd pin voltage in the s6 package and by the ov dd pin voltage in the ts8 package. 1 sck sdo t 2 t 3 t 4 t 7 t 9 t 5 z zero b11 b10 b9 b1 b0 234 (msb) hi-z state 51314 t 6 t acq t quiet t throughput t conv cs t 1 23656 f11 1 sck sdo t 2 t 3 t 4 t 7 t 8 or t 9 t 5 234 (msb) hi-z state 513141516 t 6 t acq t quiet t throughput t conv cs t 1 23656 f12 z zero b11 b10 b9 b1 b0 zero zero www.datasheet.in
LTC2365/ltc2366 16 23656f applications information sleep mode the LTC2365/ltc2366 provide a sleep mode to conserve power during inactive periods. upon power-up, holding cs high initializes the adc to sleep mode. in sleep mode, all bias circuitry is shut down and only leakage currents remain (0.1a typ). entering sleep mode the adc achieves the fastest sampling rate in operational mode (full power-up). the device can also be put into sleep mode for power savings during inactive periods. to force the LTC2365/ltc2366 into sleep mode, the user can inter- rupt the conversion process by bringing cs high between the 2nd and 10th falling edges of sck (see figures 13 and 14). if cs is brought high after the 10th falling edge and before the 16th falling edge, the device remains powered up, but the conversion is terminated and sdo returns to the high impedance state. figure 13. LTC2365/ltc2366 operational mode figure 14. LTC2365/ltc2366 entering sleep mode 12 16 14 12 10 valid data 23656 f13 sck sdo cs sck sdo 12 16 14 12 10 hi-z state cs 23656 f14 www.datasheet.in
LTC2365/ltc2366 17 23656f figure 15. LTC2365/ltc2366 exiting sleep mode applications information exiting sleep mode and power-up time to exit sleep mode, pull cs low and perform a dummy conversion. the LTC2365/ltc2366 device power up com- pletely after the 16th falling edge of sck. after powering up, the adc can continuously acquire an input signal and perform conversions as described in the serial interface section (see figure 15). the wake-up time is 333ns for the ltc2366 with a 48mhz sck and 1s for the LTC2365 with a 16mhz sck. the sample-and-hold is in hold mode while the device is in sleep mode. the adc returns to sample mode after the 1st falling edge of sck during power-up (see figure 15). power versus sampling rate figure 16 shows the power consumption of the LTC2365/ ltc2366 in operational mode. by taking the adc into sleep mode when not performing a conversion, the average power consumption of the adc decreases as the sampling rate decreases. figure 17 shows the power consumption versus sampling rate with the device in sleep mode when not performing a conversion. figure 16. power consumption vs sample rate while the device remains powered up continuously figure 17. power consumption vs sample rate while the device enters sleep mode when not performing conversions 12 16 14 12 10 1 2 16 14 12 10 invalid data valid data 23656 f15 sck sdo cs the device begins to power up the device begins to acquire input t power-up the device is fully powered up and ready to perform conversion sample rate (ksps) 0 3.0 power (mw) 3.5 4.5 5.0 5.5 2000 7.5 23656 f16 4.0 1000 500 2500 1500 3000 6.0 6.5 7.0 v dd = 3v f sck = variable 16 scks per conversion sample rate (ksps) 0 power (mw) 4 5 6 1000 23656 f17 3 2 0 250 500 750 1 8 7 v dd = 3v f sck = 48mhz www.datasheet.in
LTC2365/ltc2366 18 23656f single-ended analog input driving the analog input the analog input of the LTC2365/ltc2366 is easy to drive. the input draws only one small current spike while charg- ing the sample-and-hold capacitor at the end of conver- sion. during the conversion, the analog input draws only a small leakage current. if the source impedance of the driving circuit is low, then the input of the LTC2365/lt2366 can be driven directly. as source impedance increases, so will acquisition time. for minimum acquisition time with high source impedance, a buffer ampli? er should be used. the main requirement is that the ampli? er driving the analog input must settle after the small current spike before the next conversion starts (settling time must be less than 56ns for full throughput rate). while choosing an input ampli? er, also keep in mind the amount of noise and harmonic distortion the ampli? er contributes. choosing an input ampli? er choosing an input ampli? er is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by ampli? er from charging the sampling capacitor, choose an ampli? er that has a low output impedance (<100) at the closed-loop bandwidth frequency. for example, if an ampli? er is used in a gain of 1 and has a unitygain bandwidth of 50mhz, then the output impedance at 50mhz must be less than 100. the second requirement is that the closed-loop bandwidth must be greater than 40mhz to ensure adequate small signal settling for full throughput rate. if slower op amps are used, more time for settling can be provided by increas- ing the time between conversions. the best choice for an op amp to drive the LTC2365/ltc2366 will depend on the application. generally, applications fall into two categories: ac applications where dynamic speci? cations are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the LTC2365/ltc2366. (more detailed information is available on the linear technology website at www.linear.com.) applications information www.datasheet.in
LTC2365/ltc2366 19 23656f applications information figure 18. rc input filter ltc1566-1: low noise 2.3mhz continuous time low- pass filter. lt1630: dual 30mhz rail-to-rail voltage feedback ampli- ? er. 2.7v to 15v supplies. very high a vol , 500v offset and 520ns settling to 0.5lsb for a 4v swing. thd and noise are C93db to 40khz and below 1lsb to 320khz (a v = 1, 2v p-p into 1k, v s = 5v), making the part excellent for ac applications (to 1/3 nyquist) where rail-to-rail performance is desired. quad version is available as lt1631. lt1632: dual 45mhz rail-to-rail voltage feedback ampli- ? er. 2.7v to 15v supplies. very high a vol , 1.5mv offset and 400ns settling to 0.5lsb for a 4v swing. it is suitable for applications with a single 5v supply. thd and noise are C93db to 40khz and below 1lsb to 800khz (a v = 1, 2v p-p into 1k, v s = 5v), making the part excellent for ac applications where rail-to-rail performance is desired. quad version is available as lt1633. lt1813: dual 100mhz 750v/s 3ma voltage feedback ampli? er. 5v to 5v supplies. distortion is C86db to 100khz and C77db to 1mhz with 5v supplies (2v p-p into 500). excellent part for fast ac applications with 5v supplies. lt1801: 180mhz gbwp , C75dbc at 500khz, 2ma/ampli- ? er, 8.5nv/ hz . lt1806/lt1807: 325mhz gbwp , C80dbc distortion at 5mhz, unity-gain stable, r-r in and out, 10ma/ampli- ? er, 3.5nv/ hz . lt1810: 180mhz gbwp , C90dbc distortion at 5mhz, unity-gain stable, r-r in and out, 15ma/ampli? er, 16nv/ hz . lt1818/lt1819: 400mhz, 2500v/s, 9ma, single/dual voltage mode operational ampli? er. lt6200: 165mhz gbwp , C85dbc distortion at 1mhz, unity-gain stable, r-r in and out, 15ma/ampli? er, 0.95nv/ hz . lt6203: 100mhz gbwp , C80dbc distortion at 1mhz, unity-gain stable, r-r in and out, 3ma/amplifier, 1.9nv hz . input filtering and source impedance the noise and the distortion of the input ampli? er and other circuitry must be considered since they will add to the LTC2365/ltc2366 noise and distortion. the small-signal bandwidth of the sample-and-hold circuit is 50mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be ? ltered prior to the analog inputs to minimize noise. a simple 1-pole rc ? lter is suf? cient for many applications. for example, figure 18 shows a 47pf capacitor from a in to ground and a 51 source resistor to limit the input bandwidth to 47mhz. the 47pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sampling-glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silvermica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal ? lm surface mount resistors are much less susceptible to both problems. when high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole ? lter is required. high external source resistance, combined with the 20pf of input capacitance, will reduce the rated 50mhz bandwidth and increase acquisition time beyond 56ns. linearview is a trademark of linear technology corpration v dd gnd ltc2366 23656 f18 10f 47pf 51 6 5 4 1 2 3 cs sd0 sck a in www.datasheet.in
LTC2365/ltc2366 20 23656f applications information reference input on the ts8 package of the LTC2365/ltc2366, the voltage on the v ref pin de? nes the full-scale range of the adc. the reference voltage can range from v dd down to 1.4v. input range the analog input of the LTC2365/ltc2366 is driven single- ended with respect to gnd from a single supply. the input may swing up to v dd for the s6 package and to v ref for the ts8 package. the 0v to 2.5v range is also ideally suited for single-ended input use with v dd or v ref = 2.5v for single supply applications. if the difference between the a in input and gnd exceeds v dd for the s6 package or v ref for the ts8 package, the output code will stay ? xed at all ones, and if this difference goes below 0v, the output code will stay ? xed at all zeros. figure 19 shows the ideal input/output characteristics for the LTC2365/ltc2366. the code transitions occur mid- way between successive integer lsb values (i.e. 0.5lsb, 1.5lsb, 2.5lsb, , fs C1.5lsb). the output code is straight binary with 1lsb = v dd /4096 for the s6 package and 1lsb = v ref /4096 for the ts8 package. board layout and bypassing wire wrap boards are not recommended for high resolu- tion and/or high speed a/d converters. to obtain the best performance from the LTC2365/ltc2366, a printed circuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. the analog input should be screened by the ground plane. figure 19. LTC2365/ltc2366 transfer characteristics input voltage (v) unipolar output code 23656 f19 111...111 111...110 000...000 000...001 fs C 1lsb 1lsb 0 www.datasheet.in
LTC2365/ltc2366 21 23656f figure 20. power supply ground practice high quality tantalum and ceramic bypass capacitors should be used at the v dd and v ref pins as shown in the typical application circuit on the ? rst page of this data sheet. for optimum performance, a 10f surface mount avx capacitor with a 0.1f ceramic is recommended for the v dd pin and a 4.7f surface mount avx capacitor with a 0.1f ceramic is recommended for the v ref and ov dd pins. alternatively, 4.7f and 10f ceramic chip capacitors such as murata grm235y5v106z016 may be used. the capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. applications information figure 20 shows the recommended system ground con- nections. all analog circuitry grounds should be terminated at the LTC2365/ltc2366. the ground return from the LTC2365/ltc2366 to the power supply should be low impedance for noise free operation. digital circuitry grounds must be connected to the digital supply common. in applications where the adc data outputs and control sig- nals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the micropro- cessor to the successive approximation comparator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. 23656 f20 gnd a in v dd ca in cs sdo sck cv dd pin 1 vias to ground plane + 10f www.datasheet.in
LTC2365/ltc2366 22 23656f s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) 1.50 ?1.75 (note 4) 2.80 bsc 0.30 ?0.45 6 plcs (note 3) datum ? 0.09 ?0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ?0.90 1.00 max 0.01 ?0.10 0.20 bsc 0.30 ?0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref package description www.datasheet.in
LTC2365/ltc2366 23 23656f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637) 1.50 ?1.75 (note 4) 2.80 bsc 0.22 ?0.36 8 plcs (note 3) datum ? 0.09 ?0.20 (note 3) ts8 tsot-23 0802 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ?0.90 1.00 max 0.01 ?0.10 0.20 bsc 0.30 ?0.50 ref pin one id 3.85 max 0.52 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 www.datasheet.in
LTC2365/ltc2366 24 23656f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0408 ? printed in usa part number description comments adcs ltc1402 12-bit, 2.2msps serial adc 5v or 5v supply, 4.096v or 2.5v span ltc1403/ltc1403a 12-/14-bit, 2.8msps serial sampling adc 3v, differential input, 12mw, msop package ltc1407/ltc1407a 12-/14-bit, 3msps simultaneous sampling adc 3v, 2-channel differential, 14mw, msop package ltc1860 12-bit, 250ksps serial adc 5v supply, 1-channel, 4.3mw, msop-8 package ltc1860l 12-bit, 150ksps serial adc 3v supply, 1-channel, 1.3mw, msop-8 package ltc1861 12-bit, 250ksps serial adc 5v supply, 2-channel, 4.3mw, msop-8 package ltc1861l 12-bit, 150ksps serial adc 3v supply, 2-channel, 1.3mw, msop-8 package ltc1863 12-bit, 200ksps serial adc 8-channel adc 5v supply, 6.5mw, ssop-16 package, pin compatible to ltc1863l, ltc1867 ltc1863l 12-bit, 250ksps serial adc 8-channel adc 5v supply, 2.2mw, ssop-16 package, pin compatible to ltc1863, ltc1867l ltc1864/ltc1865 16-bit, 250ksps serial adc 5v supply, 1 and 2 channel, 4.3mw, msop package ltc1867 16-bit, 200ksps serial adc 8-channel adc 5v supply, 6.5mw, ssop-16 package, pin compatible to ltc1863, ltc1867l ltc1867l 16-bit, 175ksps serial adc 8-channel adc 3v supply, 2.2mw, ssop-16 package, pin compatible to ltc1863l, ltc1867 ltc2355/ltc2356 12-/14-bit, 3.5msps serial adc 3.3v supply, differential input, 18mw, msop package ltc2360/ltc2361/ltc2362 12-bit, 100/250/500ksps serial adc in tsot 3v supply, pin- and software-compatible to LTC2365/ltc2366 dacs ltc1592 16-bit, serial softspan ? i out dac 1lsb inl/dnl, software selectable spans ltc1666/ltc1667/ltc1668 12-/14-/16-bit, 50msps dacs 87db sfdr, 20ns settling time ltc2630 12-/10-/8-bit single v out dacs sc70 6-pin package, internal reference, 1lsb inl (12 bits) references lt1460-2.5 micropower series voltage reference 0.1% initial accuracy, 10ppm drift lt1461-2.5 precision voltage reference 0.05% initial accuracy, 3ppm drift lt1790-2.5 micropower series reference in sot-23 0.05% initial accuracy, 10ppm drift lt6660 ultra-tiny micropower series reference 2mm 2mm dfn package, 0.2% initial accuracy, 10ppm drift softspan is a trademark of linear technology corporation. typical application low-jitter clock timing with rf sine generator using clock squaring/level shifting circuit and re-timing flip-flop pre v cc 1k 1k 50 v cc nl17sz74 convert enable nc7svu04p5x master clock 0.1f conv ltc2366 control logic (fpga, cpld, dsp , etc.) d q q conv sck sdo 100 nc7svu04p5x clr 2365/2366 ta02 related parts www.datasheet.in

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